(a) Field of the Invention
The present invention relates to a pulse width filter and a filtering method. Particularly, the present invention relates to a pulse width filter preventing distortion of an input signal.
(b) Description of the Related Art
Generally, a pulse width filter transmits a pulse of an input signal when a pulse width of the input signal is more than a cut-off pulse, and does not transmit the pulse of the input signal when it is less than the cut-off pulse. The pulse width filter may be realized by using a resistor-capacitor (RC) filter.
When the pulse width of the input signal is significantly more than the cut-off pulse, the pulse of the input signal is passed through the pulse width filter without the distortion. However, when the pulse width of the input signal is slightly more than the cut-off pulse, the pulse of the input signal is distorted and is passed through the pulse width filter.
When the input signal transmits through the RC filter, a charging period in which the capacitor of the RC filter is charged and a discharging period in which the capacitor of the RC filter is discharged are generated.
For example, it is assumed that the RC filter includes an inverter input with the voltage of the capacitor, the inverter inverts the output with reference to the voltage of 2.5V, and the capacitor may be charged to 5V. The capacitor voltage starts to increase from 0V from the increasing edge of the input signal. The capacitor voltage starts to decrease from the decreasing edge of the input signal. If the capacitor voltage is more than 2.5V, the inverter outputs a low level, and if it is less than 2.5V, it outputs a high level.
If the pulse width of the input signal is sufficiently longer than the cut-off pulse, the capacitor voltage is increased to 5V, and then is decreased to 0V. Here, an increasing delay period is determined as a period that the capacitor voltage is increased from 0V to 2.5V, and a decreasing delay period is determined as a period in which the capacitor voltage is decreased from 5V to 2.5V. Accordingly, the increasing delay period and the decreasing delay period are equal to each other, and the input signal is transmitted through the RC filter without the distortion.
However, when the pulse width of the input signal is less than the cut-off pulse, the capacitor voltage cannot be increased to 5V. When the capacitor voltage reaches 2.7V, if the decreasing time of the input signal is generated, when the capacitor voltage reaches 2.5V, the inverter changes the output signal to the high level. That is, the increasing delay period is a period in which the capacitor voltage is increased from 0V to 2.5V, and the decreasing delay period is a period in which the capacitor voltage is decreased from 2.7V to 2.5V. Accordingly, the increasing delay period and the decreasing delay period are different from each other such that the input signal is distorted and transmits through the RC filter.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.